Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
The visual instruction set (VIS) in UltraSPARC
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
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The newly in troduced Microprocessor Arc hitecture for Java Computing (MAJC) supports parallelism in a hierarchy of levels: multiprocessors on chip, vertical micro threading, instruction level parallelism via a very long instruction word architecture (VLIW) and SIMD. The first implemen tation, MAJC-5200, includes some key features of MAJC to realize a high performance m ultimedia processor. Two CPUs running at 500 MHz are in tegrated into the chip to provide 6.16 GFLOPS and 12.33 GOPS with high speed in terfaces providing a peak input-output (I/O) data rate of more than 4.8 G Bytes/second. The c hip is suitable for a num ber of applications including graphics/m ultimedia processing for high-end set-top boxes, digital voice processing for telecomm unications, and advanced imaging.