Run-time scheduling and execution of loops on message passing machines
Journal of Parallel and Distributed Computing - Special issue: algorithms for hypercube computers
Vienna-Fortran/HPF Extensions for Sparse and Irregular Problems and Their Compilation
IEEE Transactions on Parallel and Distributed Systems
Microservers: a new memory semantics for massively parallel computing
ICS '99 Proceedings of the 13th international conference on Supercomputing
Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
Scientific Programming
Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
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The emergence of semiconductor fabrication technology allowing a tight coupling betw een high-density DRAM and CMOS logic on the same chip has led to the important new class of Processor-In-Memory (PIM) architectures. Furthermore, large arrays of PIMs can be arranged into massively parallel architectures. In this paper, we outline the salient features of PIM architectures and discuss macroservers, an object-based model for such machines. Subsequently, we specifically address the support for irregular problems provided by PIM arrays. The discussion concludes with a case study illustrating an approach to the solution of a sparse matrix vector multiplication.