MULTILISP: a language for concurrent symbolic computation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Actors: a model of concurrent computation in distributed systems
Actors: a model of concurrent computation in distributed systems
Concurrent programming: principles and practice
Concurrent programming: principles and practice
Introduction to parallel computing: design and analysis of algorithms
Introduction to parallel computing: design and analysis of algorithms
A methodology for programming scalable architectures
Journal of Parallel and Distributed Computing - Special issue on scalability of parallel algorithms and architectures
Pthreads programming
A design analysis of a hybrid technology multithreaded architecture for petaflops scale computation3
ICS '99 Proceedings of the 13th international conference on Supercomputing
Microservers: a new memory semantics for massively parallel computing
ICS '99 Proceedings of the 13th international conference on Supercomputing
Mapping irregular applications to DIVA, a PIM-based data-intensive architecture
SC '99 Proceedings of the 1999 ACM/IEEE conference on Supercomputing
Monitors: an operating system structuring concept
Communications of the ACM
Tera hardware-software cooperation
SC '97 Proceedings of the 1997 ACM/IEEE conference on Supercomputing
FORTRAN 95 Handbook
Extending HPF for Advanced Data-Parallel Applications
IEEE Parallel & Distributed Technology: Systems & Technology
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Opus: A Coordination Language for Multidisciplinary Applications
Scientific Programming
Scientific Programming
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The emergence of semiconductor fabrication technology allowing a tight coupling between high-density DRAM and CMOS logic on the same chip has led to the important new class of Processor-in-Memory (PIM) architectures. Recent developments provide powerful parallel processing capabilities on the chip, exploiting the facility to load wide words in single memory accesses and supporting complex address manipulations in the memory. Furthermore, large arrays of PIMs can be arranged into massively parallel architectures. In this paper, we outline the salient features of PIM architectures and describe the design of an object-based programming and execution model centered on the notion of macroservers. While generally adhering to the conventional framework of object-based computation, macroservers provide special support for the efficient control of program execution in a PIM array. This includes features for specifying the distribution and alignment of data in virtual object space, the binding of threads to data, and a future-based synchronization mechanism. We provide a number of motivating examples and give a short overview of implementation considerations.