A future-based parallel language for a general-purpose highly-parallel computer
Selected papers of the second workshop on Languages and compilers for parallel computing
Improving register allocation for subscripted variables
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
The NAS parallel benchmarks—summary and preliminary results
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
ICS '90 Proceedings of the 4th international conference on Supercomputing
A Fortran compiler for the FPS-164 scientific computer
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Recognizing and Parallelizing Bounded Recurrences
Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing
IPPS '95 Proceedings of the Workshop on Job Scheduling Strategies for Parallel Processing
Retrospective: Monsoon: an explicit token-store architecture
25 years of the international symposia on Computer architecture (selected papers)
Communications of the ACM
Tuning Compiler Optimizations for Simultaneous Multithreading
International Journal of Parallel Programming - Special issue on the 30th annual ACM/IEEE international symposium on microarchitecture, part II
Crash Analysis on the Tera MTA
IEEE Computational Science & Engineering
Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
An Implementation of the SSF Scalable Simulation Framework on the Cray MTA
Proceedings of the seventeenth workshop on Parallel and distributed simulation
"MAMA!": a memory allocator for multithreaded architectures
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
A case study of multi-threading in the embedded space
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
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The development of Tera's MTA system was unusual. It respected the need for fast hardware and large shared memory, facilitating execution of the most demanding parallel application programs. But at the same time, it met the need for a clean machine model enabling calculated compiler optimizations and easy programming; and the need for novel architectural features necessary to support fast parallel system software. From its inception, system and application needs have molded the MTA architecture. The result is a system that offers high performance and ease of programming by virtue not only of fast physical hardware and flat shared memory, but also of the streamlined software systems that well utilize the features of the architecture intended to support them.