Designing the Agassiz Compiler for Concurrent Multithreaded Architectures

Authors:
Bess Zheng;Jenn-Yuan Tsai;B. Y. Zhang;T. Chen;B. Huang;J. H. Li;Y. H. Ding;J. Liang;Y. Zhen;Pen-Chung Yew;Chuan-Qi Zhu
Affiliations:
-;-;-;-;-;-;-;-;-;-;-
Venue:
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Year:
1999

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Abstract

In this paper, we present the overall design of the Agassiz compiler [1]. The Agassiz compiler is an integrated compiler targeting the concurrent multithreaded architectures [12,13]. These architectures can exploit both looplevel and instruction-level parallelism for general-purpose applications (such as those in SPEC benchmarks). They also support various kinds of control and data speculation, runtime data dependence checking, and fast synchronization and communication mechanisms. The Agassiz compiler has a loop-level parallelizing compiler as its front-end and an instruction-level optimizing compiler as its back-end to support such architectures. In this paper, we focus on the IR design of the Agassiz compiler and describe how we support the front-end analyses, various optimization techniques, and source-to-source translation.