Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Handbook of theoretical computer science (vol. B)
Combining functional programming and hardware verification (invited talk)
ICFP '00 Proceedings of the fifth ACM SIGPLAN international conference on Functional programming
Justifying proofs using memo tables
Proceedings of the 2nd ACM SIGPLAN international conference on Principles and practice of declarative programming
Symbolic Model Checking
Communication and Concurrency
An Optimizing Compiler for Efficient Model Checking
FORTE XII / PSTV XIX '99 Proceedings of the IFIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XII) and Protocol Specification, Testing and Verification (PSTV XIX)
Efficient Model Checking Using Tabled Resolution
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
XMC: A Logic-Programming-Based Verification Toolset
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
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The PARMC system performs model checking for systems described in the XL language, a variant of CCS. Extending previous work by Dong and Ramakrishnan that compiled XL specifications into an optimized transition relation, we take their transition relation and compile it into S-code, producing instructions for a new lightweight engine S that was custom designed for PARMC. Difficult constructs are handled by the XSB logic programming engine, enabling both generality (from XSB) and speed (from S). States are maintained in a compressed representation, also improving memory utilization. Experiments were performed and showed that the anticipated speed and memory improvements were achieved.