Analytic derivation of processor potential utilization in straight line, ring, square mesh, and hypercube networks

Authors:
R. G. Born;J. R. Kenevan
Affiliations:
Illinois Institute of Technology;Illinois Institute of Technology
Venue:
SIGMETRICS '88 Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Year:
1988

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Abstract

In multicomputer architectures, in which processors communicate through message-passing, the overhead encountered because of the need to relay messages can significantly affect performance. Based upon some simplifying assumptions including the rate at which a processor generates messages being proportional to its current potential utilization, processor utilizations are analytically derived in matrix form for a bidirectional straight line and square mesh. In addition, closed form derivations are provided for a unidirectional ring and an n-dimensional hypercube. Finally, the theoretical results are found to be in close agreement with discrete-event simulations of the four architectures.