The influence of caches on the performance of heaps
Journal of Experimental Algorithmics (JEA)
Simple randomized mergesort on parallel disks
Parallel Computing - Special double issue: parallel I/O
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Random permutations on distributed, external and hierarchical memory
Information Processing Letters
The influence of caches on the performance of sorting
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Performance Analysis of Cache Memories
Journal of the ACM (JACM)
Worst-Case External-Memory Priority Queues
SWAT '98 Proceedings of the 6th Scandinavian Workshop on Algorithm Theory
The Buffer Tree: A New Technique for Optimal I/O-Algorithms (Extended Abstract)
WADS '95 Proceedings of the 4th International Workshop on Algorithms and Data Structures
ESA '98 Proceedings of the 6th Annual European Symposium on Algorithms
First draft of a report on the EDVAC
First draft of a report on the EDVAC
Efficient Sorting Using Registers and Caches
WAE '00 Proceedings of the 4th International Workshop on Algorithm Engineering
Optimised Predecessor Data Structures for Internal Memory
WAE '01 Proceedings of the 5th International Workshop on Algorithm Engineering
Analysing the Cache Behaviour of Non-uniform Distribution Sorting Algorithms
ESA '00 Proceedings of the 8th Annual European Symposium on Algorithms
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The cache hierarchy prevalent in todays high performance processors has to be taken into account in order to design algorithms which perform well in practice. We start from the empirical observation that external memory algorithms often turn out to be good algorithms for cached memory. This is not self evident since caches have a fixed and quite restrictive algorithm choosing the content of the cache. We investigate the impact of this restriction for the frequently occurring case of access to multiple sequences. We show that any access pattern to k = Θ(M/B1+1/a) sequential data streams can be efficiently supported on an a-way set associative cache with capacity M and line size B. The bounds are tight up to lower order terms.