Statecharts: A visual formalism for complex systems
Science of Computer Programming
Combining UML and formal notations for modelling real-time systems
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
A polymodal semantics for VHDL
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
A Comparison of Statecharts Variants
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
Formal verification of vhdl designs using temporal logics
Formal verification of vhdl designs using temporal logics
Reasoning about real-time statecharts in the presence of semantic variations
Proceedings of the 20th IEEE/ACM international Conference on Automated software engineering
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This paper describes a formal framework for expressing the semantics of UML augmented with real-time constructs. The approach is based on a two-dimensional temporal logic to independently capture control-flow as well as time-flow. The goal is to provide a simple, intuitive, and validatable semantics that can be used for further formal analysis.