Theory of linear and integer programming
Theory of linear and integer programming
Control generation in the design of processor arrays
Journal of VLSI Signal Processing Systems - Parallel processing on VLSI arrays
Partitioning of processor arrays: a piecewise regular approach
Integration, the VLSI Journal - Special issue on algorithms and architectures
Resource constrained scheduling of uniform algorithms
Journal of VLSI Signal Processing Systems
Parametric Analysis of Polyhedral Iteration Spaces
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
The Organization of Computations for Uniform Recurrence Equations
Journal of the ACM (JACM)
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Design Space Exploration for Massively Parallel Processor Arrays
PaCT '01 Proceedings of the 6th International Conference on Parallel Computing Technologies
Loop Parallelization in the Polytope Model
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Complexity of matrix product on modular linear systolic arrays for algorithms with affine schedules
Journal of Parallel and Distributed Computing
Experiences with enumeration of integer projections of parametric polytopes
CC'05 Proceedings of the 14th international conference on Compiler Construction
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We present a new methodology for controlling the space-time behavior of VLSI and FPGA-based processor arrays. The main idea is to generate simple local control elements which take control over the activeness of each attached processor element. Each control element thereby propagates a "start" and a "stop execution" signal to its neighbors. We show that our control mechanism is much more efficient than existing approaches because 1) only two control signals (start/stop) are required, 2) no extension of the computation space is necessary. 3) By the local propagation of just one start/stop signal, energy is saved as processing elements are only active between the time they have received the start signal and the time they have received the stop signal. Our methodology is applicable to one- and multi-dimensional processor arrays and is based on local control signal propagation. We provide a theoretical analysis of the overhead caused by the control structure.