Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Future Generation Computer Systems
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Previous models for performance evaluation of multistage switches have been neither accurate enough nor based on realistic assumptions regarding the correlation of the blocked cells in successive stages of the switch. In this paper, a new analytical model which permits an accurate analysis of multistage switches is proposed. The new model reflects the behavior of blocked cells, and takes into account the fact that a blocked cell always hunts for the same output link in successive cycles.