Vector ISA Extension for Sparse Matrix-Vector Multiplication

Authors:
Stamatis Vassiliadis;Sorin Cotofana;Pyrrhos Stathis
Affiliations:
-;-;-
Venue:
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Year:
1999

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Abstract

In this paper we introduce a vector ISA extension to facilitate sparse matrix manipulation on vector processors (VPs). First we introduce a new Block Based Compressed Storage (BBCS) format for sparse matrix representation and a Block-wise Sparse Matrix-Vector Multiplication approach. Additionally, we propose two vector instructions, Multiple Inner Product and Accumulate (MIPA) and LoaD Section (LDS), specially tuned to increase the VP performance when executing sparse matrix-vector multiplications.