Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Checking combinational equivalence of speed-independent circuits
Formal Methods in System Design
Static Partial Order Reduction
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Concurrent rewriting semantics and analysis of asynchronous digital circuits
WRLA'10 Proceedings of the 8th international conference on Rewriting logic and its applications
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We describe two approaches to use the model checking tool COSPAN to check the hazard freedom in speed-independent circuits. First, we propose a straight forward approach to implement a speed-independent circuit in S/R. Second, we propose a reduction technique over the first approach by restricting the original system with certain constraints. This reduction is implemented on the top of COSPAN which also applies its own reductions, including symbolic representation (BDD).