An empirical comparison of priority-queue and event-set implementations
Communications of the ACM
Calendar queues: a fast 0(1) priority queue implementation for the simulation event set problem
Communications of the ACM
IEEE Transactions on Software Engineering
Fishspear: a priority queue algorithm
Journal of the ACM (JACM)
The influence of caches on the performance of heaps
Journal of Experimental Algorithmics (JEA)
Simple randomized mergesort on parallel disks
Parallel Computing - Special double issue: parallel I/O
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The influence of caches on the performance of sorting
SODA '97 Proceedings of the eighth annual ACM-SIAM symposium on Discrete algorithms
Introduction to Algorithms
Worst-Case External-Memory Priority Queues
SWAT '98 Proceedings of the 6th Scandinavian Workshop on Algorithm Theory
The Buffer Tree: A New Technique for Optimal I/O-Algorithms (Extended Abstract)
WADS '95 Proceedings of the 4th International Workshop on Algorithms and Data Structures
ESA '98 Proceedings of the 6th Annual European Symposium on Algorithms
First draft of a report on the EDVAC
First draft of a report on the EDVAC
Performance Engineering Case Study: Heap Construction
WAE '99 Proceedings of the 3rd International Workshop on Algorithm Engineering
An Experimental Study of Priority Queues in External Memory
WAE '99 Proceedings of the 3rd International Workshop on Algorithm Engineering
LEDA-SM Extending LEDA to Secondary Memory
WAE '99 Proceedings of the 3rd International Workshop on Algorithm Engineering
Efficient Sorting Using Registers and Caches
WAE '00 Proceedings of the 4th International Workshop on Algorithm Engineering
External Memory Data Structures
ESA '01 Proceedings of the 9th Annual European Symposium on Algorithms
Balanced allocation and dictionaries with tightly packed constant size bins
ICALP'05 Proceedings of the 32nd international conference on Automata, Languages and Programming
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The cache hierarchy prevalent in todays high performance processors has to be taken into account in order to design algorithms which perform well in practice. We advocates the approach to adapt external memory algorithms to this purpose. We exemplify this approach and the practical issues involved by engineering a fast priority queue suited to external memory and cached memory which is based on k-way merging. It improves previous external memory algorithms by constant factors crucial for transferring it to cached memory. Running in the cache hierarchy of a workstation the algorithm is at least two times faster than an optimized implementation of binary heaps and 4-ary heaps for large inputs.