Design and validation of computer protocols
Design and validation of computer protocols
Property preserving abstractions for the verification of concurrent systems
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Model checking
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Systems Engineering Using SDL-92
Systems Engineering Using SDL-92
Validating SDL Specifications: an Experiment
Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX
Embedding a Dialect of SDL in PROMELA
Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking
Integrating Real Time into Spin: A Prototype Implementation
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Formal Verification of SDL Systems at the Siemens Mobile Phone Department
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Verifying Large SDL-Specifications Using Model Checking
SDL '01 Proceedings of the 10th International SDL Forum Copenhagen on Meeting UML
Formal Specification and Analysis of Timing Properties in Software Systems
FASE '09 Proceedings of the 12th International Conference on Fundamental Approaches to Software Engineering: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009
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Industrial-size specifications/models (whose state space is often infinite) can not be model checked in a direct way -- a verification model of a system is model checked instead. Program transformation is a way to build a finite-state verification model that can be submitted to a model checker. Abstraction is another technique that can be used for the same purpose. This paper presents a transformation of SDL timers aimed at the reduction of the infinite domain of timer values to a finite one with preserving the behaviour of a system. A timer abstraction is proposed to further reduce the state space. We discuss the ideas behind these transformations and argue their correctness.