IEEE Transactions on Computers
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The predictability of data values
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
High-Performance RISC Microprocessors
IEEE Micro
Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
An Architecture Framework for Introducing Predicated Execution into Embedded Microprocessors
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
Global Context-Based Value Prediction
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Efficacy and Performance Impact of Value Prediction
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Low-Cost Value Predictors Using Frequent Value Locality
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
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The growing market of embedded systems and applications has led to the making of more general embedded processors, with some features traditionally associated with general-purpose microprocessors. Following this trend, recent research has tried to incorporate into embedded processors the newest techniques to break down ILP limits. Value speculation is a recent technique not yet considered in the context of embedded processors, and the goal of the present work is to analyse the performance potential of this technique within this scope.