MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance
VECPAR '00 Selected Papers and Invited Talks from the 4th International Conference on Vector and Parallel Processing
Extending an embedded RISC microprocessor for efficient translation based Java execution
Microprocessors & Microsystems
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Designing RISC microprocessor cores for high-performance embedded systems requires a different perspective from system and processor architects. SandCraft, Inc. has developed its latest generation MIPS cores, emphasizing the need for a high degree of leverage between members of the microprocessor family. The Montage architecture introduces some novel features, such as accommodating extensions for added flexibility, which allow the processors to meet customer requirements. Already two family members, the SR1 and SR1-GX, have been implemented using the Montage architecture. These two cores were extensively modeled to verify their capabilities. The SR1 is optimized for high integer and floating-point performance, while the SR1-GX is an SR1 extended with a vector/scalar floating-point capability for accelerating 3D graphics applications.