Timing assumptions and verification of finite-state concurrent systems
Proceedings of the international workshop on Automatic verification methods for finite state systems
Completing the temporal picture
Selected papers of the 16th international colloquium on Automata, languages, and programming
Theoretical Computer Science
ICALP '97 Proceedings of the 24th International Colloquium on Automata, Languages and Programming
Symbolic Verification of Lossy Channel Systems: Application to the Bounded Retransmission Protocol
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Synthesis of Linear Ranking Functions
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Verifying Universal Properties of Parameterized Networks
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
On-the-Fly Analysis of Systems with Unbounded, Lossy FIFO Channels
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Liveness and Acceleration in Parameterized Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Symbolic Verification with Periodic Sets
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
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We address the problem of verifying safety and liveness properties for infinite-state systems, using symbolic reachability analysis. The models we consider are fair parametric extended automata, i.e., counter automata with parametric guards, supplied with fairness conditions on their transitions. In previous work, we shown that symbolic reachability analysis using acceleration techniques can be used to generate finite abstractions (symbolic graphs) of the original infinite-state model. In this paper, we show that this analysis can be also used to introduce fairness conditions on the generated abstract model allowing to model-check liveness properties. We show first how to translate faithfully the fairness conditions of the infinite-state original model to conditions on the generated finite symbolic graph. Then, we show that we can also synthesize automatically new fairness conditions allowing to eliminate infinite paths in the symbolic graph which do not correspond to valid behaviours in the original model. These infinite paths correspond to abstractions of boundedly iterable (nested) loops. We show techniques allowing to decide this bounded iterability for a class of components in the symbolic graph. We illustrate the application of these techniques to nontrivial examples.