Fairness
Hierarchical correctness proofs for distributed algorithms
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
Communication and Concurrency
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Verifying Abstractions of Timed Systems
CONCUR '96 Proceedings of the 7th International Conference on Concurrency Theory
Checking for Language Inclusion Using Simulation Preorders
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Using mappings to prove timing properties
Distributed Computing
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As many processes concurrently behave and timing constraints are strict in real-time systems, it is difficult to design real-time systems. For this recison, a hiercirchical design method is useful. In the hierarchical design method, it is important to verify whether the low level specification satisfies the high level specification or not. In general, the language inclusion verification method is useful for verifying it. But, as nondeterministic timed automata are not closed under complementation, it is impossible to use the language inclusion verification method. In this paper, we propose the hierarchical design method based on timed simulation method. Especially, we generalize existing timed simulation methods and propose a safety timed simulation relation and a ∃-liveness timed simulation relation, a ∀-Iiveness timed simulation relation. Finally, we show our proposed method effective by some example.