Design and validation of computer protocols
Design and validation of computer protocols
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
Verification of Real-Time Systems using Linear Relation Analysis
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Automatic Generation of Invariants
Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
Automatic predicate abstraction of C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Predicate abstraction for software verification
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Verifying a Sliding Window Protocol using PVS
FORTE '01 Proceedings of the IFIP TC6/WG6.1 - 21st International Conference on Formal Techniques for Networked and Distributed Systems
STG: A Symbolic Test Generation Tool
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Testing Concurrent Systems: A Formal Approach
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Automated Test and Oracle Generation for Smart-Card Applications
E-SMART '01 Proceedings of the International Conference on Research in Smart Cards: Smart Card Programming and Security
Experiments in Theorem Proving and Model Checking for Protocol Verification
FME '96 Proceedings of the Third International Symposium of Formal Methods Europe on Industrial Benefit and Advances in Formal Methods
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Abstract and Model Check While You Prove
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Test Generation Derived from Model-Checking
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CADP - A Protocol Validation and Verification Toolbox
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
An Approach to Symbolic Test Generation
IFM '00 Proceedings of the Second International Conference on Integrated Formal Methods
Formal Test Automation: A Simple Experiment
Proceedings of the IFIP TC6 12th International Workshop on Testing Communicating Systems: Method and Applications
Using the Bandera Tool Set to Model-Check Properties of Concurrent Java Software
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
CASTING: A Formally Based Software Test Generation Method
ICFEM '97 Proceedings of the 1st International Conference on Formal Engineering Methods
A Survey of Program Slicing Techniques.
A Survey of Program Slicing Techniques.
Automated Test Generation and Verified Software
Verified Software: Theories, Tools, Experiments
Complete Test Graph Synthesis For Symbolic Real-time Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
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Applying formal methods to testing has recently become a popular research topic. In this paper we explore the opposite approach, namely, applying testing techniques to formal verification. The idea is to use symbolic test generation to extract subgraphs (called components) from a specification and to perform the verification on the components rather than on the whole system. This may considerably reduce the verification effort and, under reasonable sufficient conditions, a safety property verified on a component also holds on the whole specification. We demonstrate the approach by verifying an electronic purse system using our symbolic test generation tool STG and the PVS theorem prover.