Communicating sequential processes
Communicating sequential processes
Mechanizing CSP Trace Theory in Higher Order Logic
IEEE Transactions on Software Engineering
Formal Verification of Ada Programs
IEEE Transactions on Software Engineering
Larch: languages and tools for formal specification
Larch: languages and tools for formal specification
Abstractions for Software Architecture and Tools to Support Them
IEEE Transactions on Software Engineering - Special issue on software architecture
Specification and Analysis of System Architecture Using Rapide
IEEE Transactions on Software Engineering - Special issue on software architecture
Formalizing architectural connection
ICSE '94 Proceedings of the 16th international conference on Software engineering
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Principles of Programming Languages
Principles of Programming Languages
Hardware Design and Simulation in Val-VHDL
Hardware Design and Simulation in Val-VHDL
Performance Modeling Using PDL
Computer
An Event-Based Architecture Definition Language
IEEE Transactions on Software Engineering
8.4: SAVANT/TyVIS/WARPED: Components for the Analysis and Simulation of VHDL
IVC-VIUF '98 Proceedings of the International Verilog HDL Conference and VHDL International Users Forum
A Case Study in Architectural Modelling: The AEGIS System
IWSSD '96 Proceedings of the 8th International Workshop on Software Specification and Design
On the language design and semantic foundation of lcl, a larch/c interface specification language
On the language design and semantic foundation of lcl, a larch/c interface specification language
The Larch Family of Specification Languages
IEEE Software
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This paper provides an overview of the VSPEC behavioral interface specification language for VHDL. Although operational specification language such as VHDL provide exceptional specification capabilities, at the systems requirements level the operational style is a hindrance. vspec provides VHDL users with a declarative mechanism for defining functional requirements and performance constraints. In the tradition of behavioral interface specification languages, VSPEC adds clauses to the VHDL entity construct allowing axiomatic specification of functional requirements. Because system constraints play an ever increasing role in systems design, VSPEC also provides performance constraint specification capability. This paper presents the basics of VSPEC, its semantics, semantic analysis, and briefly describes current and future applications.