Journal of the ACM (JACM)
Model-checking in dense real-time
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Real-time logics: complexity and expressiveness
Information and Computation - Special issue: selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
The benefits of relaxing punctuality
Journal of the ACM (JACM)
Specification of realtime systems using ASTRAL
IEEE Transactions on Software Engineering
Reversal-Bounded Multicounter Machines and Their Decision Problems
Journal of the ACM (JACM)
From Timed Automata to Logic - and Back
MFCS '95 Proceedings of the 20th International Symposium on Mathematical Foundations of Computer Science
Bebop: A Symbolic Model Checker for Boolean Programs
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
ICALP '92 Proceedings of the 19th International Colloquium on Automata, Languages and Programming
On the Expressiveness of Real and Integer Arithmetic Automata (Extended Abstract)
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
On Presburger Liveness of Discrete Timed Automata
STACS '01 Proceedings of the 18th Annual Symposium on Theoretical Aspects of Computer Science
Reachability Analysis of Pushdown Automata: Application to Model-Checking
CONCUR '97 Proceedings of the 8th International Conference on Concurrency Theory
Timed Automata and the Theory of Real Numbers
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Decidable Approximations on Generalized and Parameterized Discrete Timed Automata
COCOON '01 Proceedings of the 7th Annual International Conference on Computing and Combinatorics
Specifying Timed State Sequences in Powerful Decidable Logics and Timed Automata
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
HYTECH: The Cornell HYbrid TECHnology Tool
Hybrid Systems II
State Clock Logic: A Decidable Real-Time Logic
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Binary Reachability Analysis of Discrete Pushdown Timed Automata
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Lectures on Embedded Systems, European Educational Forum, School on Embedded Systems
Multiple Counters Automata, Safety Analysis and Presburger Arithmetic
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CIAA '01 Revised Papers from the 6th International Conference on Implementation and Application of Automata
ATVA'10 Proceedings of the 8th international conference on Automated technology for verification and analysis
Model checking recursive programs with numeric data types
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Infinite computation, co-induction and computational logic
CALCO'11 Proceedings of the 4th international conference on Algebra and coalgebra in computer science
Verifying complex continuous real-time systems with coinductive CLP(R)
LATA'10 Proceedings of the 4th international conference on Language and Automata Theory and Applications
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We consider pushdown timed automata (PTAs) that are timed automata (with dense clocks) augmented with a pushdown stack. A configuration of a PTA includes a control state, dense clock values and a stack word. By using the pattern technique, we give a decidable characterization of the binary reachability (i.e., the set of all pairs of configurations such that one can reach the other) of a PTA. Since a timed automaton can be treated as a PTA without the pushdown stack, we can show that the binary reachability of a timed automaton is definable in the additive theory of reals and integers. The results can be used to verify a class of properties containing linear relations over both dense variables and unbounded discrete variables. The properties previously could not be verified using the classic region technique nor expressed by timed temporal logics for timed automata and CTL* for pushdown systems.