Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations

Authors:
Stephen J. Spinks;C. D. Chalk;Ian M. Bell;Mark Zwolinski
Affiliations:
-;-;-;-
Venue:
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Year:
1997

Citing 0
Cited 4

Fault Simulation for Analog Circuits Under Parameter Variations

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Speed-up of High Accurate Analog Test Stimulus Optimization

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current

Journal of Electronic Testing: Theory and Applications
The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach

Journal of Electronic Testing: Theory and Applications

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Abstract

The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.