Optimal temporal partitioning and synthesis for reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Algorithms for High-Level Synthesis
IEEE Design & Test
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
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This paper presents an automatic design synthesis technique for Dynamically Reconfigurable Logic (DRL) systems. Given an input behavioural algorithm, a target technology library server and a set of design constraints, the synthesis algorithm will generate a DRL design solution in a form of a 3D floorplan and a design schedule. The technique optimises the design solution in a multiple-objective design search space, while making realistic assumptions about the implementation reconfiguration overheads. Partial reconfiguration is considered if such a feature is available in the target technology. Simultaneous consideration of the multiple design objectives at various abstraction levels, together with a realistic estimation of the reconfiguration overheads, guarantees the feasibility of the automatically generated solutions. The presented approach is based on generic algorithms with problem-specific coding and operators. The performance of the algorithm was tested using a selection of small benchmarks within the DYNASTY Framework.