GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Solving Boolean Satisfiability with Dynamic Hardware Configurations
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
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Solving Boolean satisfiability problems in reconfigurable hardware is an area of great research interest. Originally, reconfigurable hardware was used to map each problem instance and thus exploit maximum parallelism in evaluation of variable assignments. However, techniques to greatly reduce the search space require dynamic reconfiguration, and make regular mappings more desirable. Unfortunately, using a regular mapping constrains the parallelism in assignment evaluation. The architectures that have emerged choose either custom mapping and maximum parallelism or regular mapping and the promise of significant decreases in the search space. We propose a framework that can exploit both. Our framework uses a regular mapping while introducing a scalable parallel architecture. Using our approach, speedups of up to one order of magnitude over current state-of-the-art reconfigurable hardware solvers have been obtained.