A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Introduction to algorithms
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Solving Boolean Satisfiability with Dynamic Hardware Configurations
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Parallel Pipelined SAT Solver for FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Solving Satisfiability Problems on FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
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FPGAs are a promising technology for accelerating SAT solvers. Besides their high density, fine granularity, and massive parallelism, FPGAs provide the opportunity for run-time customization of the hardware based on the given SAT instance. In this paper, a parallel deduction engine is proposed for backtrack search algorithms. The performance of the deduction engine is critical to the over-all performance of the algorithm since, for any moderate SAT instance, millions of implications are derived.We propose a novel approach in which, p, the amount of parallelization of the engine is fine-tuned during problem solving in order to optimize performance. Not only the hardware is initially customized based on the input instance, but it is also dynamically modified in terms of p based on the knowledge gained during solving the SAT instance. Compared with conventional deduction engines that correspond to p = 1, we demonstrate speedups in the range of 2.87 - 5.44 for several SAT instances.