Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
High-speed policy-based packet forwarding using efficient multi-dimensional range matching
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Packet classification on multiple fields
Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Managing IP Networks With Cisco Routers
Managing IP Networks With Cisco Routers
Algorithms for Improving the Dependability of Firewall and Filter Rule Lists
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
An FPGA-based coprocessor for ATM firewalls
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Specialized Hardware for Deep Network Packet Filtering
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Proceedings of the Conference on Design, Automation and Test in Europe
Improving NFA-based signature matching using ordered binary decision diagrams
RAID'10 Proceedings of the 13th international conference on Recent advances in intrusion detection
Fast, memory-efficient regular expression matching with NFA-OBDDs
Computer Networks: The International Journal of Computer and Telecommunications Networking
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Network packet classification is an important function for firewalls and filters. Packet classification based on transport-layer headers is widely used, and is specified by providing the filter with a list of rules. The cost of lookup may become a bottleneck in network performance. We present a novel technique for packet classification using FPGAs that exploits the reprogrammable nature of FPGAs. The rules are converted into a boolean expression which is directly implemented as a circuit on an FPGA. This approach is cheaper and simpler than previous hardware implementations, and we have had good experimental results.