FPGA QAM Demodulator Design

  • Authors:
  • Chris Dick;Fred Harris

  • Affiliations:
  • -;-

  • Venue:
  • FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
  • Year:
  • 2002

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Abstract

Bandwidth efficient communication systems employ highorder modulation schemes like M-ary QAM modulation for reasons of spectral efficiency. Many sophisticated signal processing algorithms are implemented in a QAM demodulator, including adaptive equalization, timing recovery, carrier recovery, automatic gain control and digital down conversion to name a few. This paper examines the FPGA implementation of the adaptive equalizer and carrier recovery loop for a 50 Mbps 16-QAM receiver.