Computer Vision, Graphics, and Image Processing
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
Programming in PROLOG
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
High level programming for real time FPGA based video processing
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
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This paper presents a Hardware Development Environment based on the logic programming language Prolog. Central to this environment are a hardware description notation called HIDE, and a high level generator, which takes an application specific, high level algorithm description, and translates it into a HIDE description. The latter describes scaleable and parameterised architectures using a small set of Prolog constructors. EDIF netlists can be automatically generated from HIDE descriptions. The high-level algorithm descriptions are based on a library of reusable Hardware Skeletons. A hardware skeleton is a parameterised description of a task-specific architecture, to which the user can supply parameters such as values, functions or even other skeletons. A skeleton contains built-in rules, written in Prolog that will apply optimisations specific to the target hardware at the implementation phase. This is the key towards the satisfaction of the dual requirement of high-level abstract hardware design and hardware efficiency.