Elimination of bottlenecks in dynamic dataflow processors

Authors:
K. B. Irani;K. Q. Luc
Affiliations:
Division of Computer Science and Engineering, Department of Electrical Engineering and Comptuer Science, The University of Michigan, Ann Arbor, MI;Division of Computer Science and Engineering, Department of Electrical Engineering and Comptuer Science, The University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Year:
1988

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Abstract

A key component of a dynamic dataflow processor, the matching unit, has been identified as a major bottleneck. An alternate implementation for the matching unit is presented. This implementation increases the operating bandwidth of the unit by allowing token matching operations to be done concurrently. The adoption of the proposed implementation also reveals throughput limitations of other units within the processor. As a result, a new configuration for a dynamic dataflow processor is proposed. We believe that the proposed processor is cost-effective, gives high performance, and is capable of incremental performance improvement.