Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe Card
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model
Journal of Electronic Testing: Theory and Applications
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Reducing test costs is a constant issue for semiconductormanufacturers. One key to reducing test cost is reducingtest time. Parallel testing is widely employed for thispurpose, but the cost of the parallel test system itself isgenerally high, and simpler test systems would bringfurther substantial reductions in test cost. We havedeveloped test system structures in which the number ofdigitizers is much smaller than the number of devicefunctions being tested, as a means of reducing the cost ofthe parallel test system. Here we describe three of these testsystem configurations and an investigation of theirperformance in parallel testing of one or two two-channelmixed-signal devices. The results demonstrate thepossibility of relatively low-cost, efficient parallel testingof two or more two-channel DACs with one digitizer, basedon a mixed-signal tester currently in general use.