Computing binary decision diagrams for VHDL data types
EURO-DAC '94 Proceedings of the conference on European design automation
Verification of a production cell using an automatic verification environment for VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Abstract interpretation of reactive systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Formal Methods in System Design - Special issue on The First Federated Logic Conference (FLOC'96), part II
Finding Feasible Counter-examples when Model Checking Abstracted Java Programs
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Reducing Model Checking from Multi-valued {\rm CTL}^{\ast} to {\rm CTL}^{\ast}
CONCUR '02 Proceedings of the 13th International Conference on Concurrency Theory
On Designated Values in Multi-valued CTL^* Model Checking
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
Symbolic model checking for temporal-epistemic logics
ACM SIGACT News
Deductive multi-valued model checking
ICLP'05 Proceedings of the 21st international conference on Logic Programming
Symbolic model checking for temporal-epistemic logic
Logic Programs, Norms and Action
On Designated Values in Multi-valued CTL^* Model Checking
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P 2003)
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