Verification of a production cell using an automatic verification environment for VHDL

Petri nets as intermediate representation between VHDL and symbolic transition systems

EURO-DAC '94 Proceedings of the conference on European design automation

Computing binary decision diagrams for VHDL data types

EURO-DAC '94 Proceedings of the conference on European design automation

Model checking in industrial hardware design

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Translating VHDL into functional symbolic finite-state models

Formal Methods in System Design - Special issue on VHDL semantics

Verification of a production cell controller using symbolic timing diagrams

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Specification and verification of VHDL-based system-level hardware designs

Specification and validation methods

Symbolic Model Checking

Symbolic Model Checking

Model Checking Using Adaptive State and Data Abstraction

CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification