Introduction to algorithms
Compact vector generation for accurate power simulation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Improving the efficiency of power simulators by input vector compaction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Hierarchical sequence compaction for power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power invariant vector sequence compaction
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Sequence compaction for power estimation: theory and practice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Simulation-based power estimation is commonly used for its high accuracy despite excessive computation times. Techniques have been proposed to speed it up by compacting an input sequence while preserving its power-consumption characteristics. We propose a novel method to compact a sequence that preserves transition frequencies. We prove the problem is NP-complete, and propose a graph model to reduce it to that of finding a heaviest-weighted trail, and a heuristic utilizing this model. We also propose using multiple sequences for better accuracy with even shorter sequences. Experiments show that power dissipation can be estimated with an error of only 2.3%, while simulation times are reduced by 10. Proposed methods generate solutions that effectively preserve transition frequencies and that are very close to optimal. Experiments also show that multiple sequences grant more accurate results with even shorter sequences.