Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array

  • Authors:

  • Jianhua Gan;Shouli Yan;Jacob Abraham

  • Affiliations:

  • Cirrus Logic, Inc., Austin, TX;University of Texas at Austin, Austin, TX;University of Texas at Austin, Austin, TX

  • Venue:
  • Proceedings of the 13th ACM Great Lakes symposium on VLSI
  • Year:
  • 2003

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Abstract

The design and modeling of a high performance successive approximation analog-to-digital converter (ADC) using non-binary capacitor array are presented in this paper. A non-binary capacitor array with 20 capacitors is used to design a 16-bit, 1.5 mega samples per second (MSPS) successive approximation ADC. A perceptron learning rule, originally developed for Artificial Intelligence applications, is used as the capacitor calibration algorithm. The system architecture and the circuit design for the capacitor array, the sampling network and the high performance comparator are discussed. The capacitor weights are adaptively calibrated to match the physical capacitors with better than 22-bit accuracy. Capacitor matching is not a limiting factor to the accuracy. Various sources of noise, interference and distortion are modeled to evaluate their effects and to ensure the robustness of the calibration algorithm. This architecture is especially suitable for mixed-signal VLSI in the Nanometer Era because it relaxes the matching requirement on analog circuitry.