Low-power and area-efficient FIR filter implementation suitable for multiple taps

Authors:
Kyung-Saeng Kim;Kwyro Lee
Affiliations:
Hynix Semiconductor, Inc., Seoul, Korea;MICROS Research Center and the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Taejon, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Year:
2003

Citing 1
Cited 3

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A hardware-efficient programmable FIR processor using input-data and tap folding

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An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

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FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

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Abstract

This paper describes a 32-tap finite impulse response (FUR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-µm CMOS technology with three levels of metal. The chip that occupies 2.3 × 2.5 mm2 of silicon area has an operating frequency of 20 MHz and consumes 75 mW at Vdd = 3.3 V.