Optimistic parallel simulation of a large-scale view storage system

  • Authors:
  • Garrett Yaun;Christopher D. Carothers;Sibel Adali;David Spooner

  • Affiliations:
  • Department of Computer Science, Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY;Department of Computer Science, Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY;Department of Computer Science, Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY;Department of Computer Science, Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY

  • Venue:
  • Future Generation Computer Systems - Selected papers from CCGRID 2002
  • Year:
  • 2003

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Abstract

In this paper, we present the design and implementation of a complex view storage system model. Here, a hierarchy of view storage servers are connected to an array of client-side local disks. The term view refers to the output or result of a query made on the part of an application that is executing on a client machine. These queries can to be arbitrarily complex and formulated using SQL. The goal of this system is to reduce the turnaround time of queries by exploiting locality both at the local disk level as well as between clients and servers prior to making the request to the highest level database server. This model has been designed for execution with an optimistic simulation engine. One of the primary drawbacks of this parallel synchronization mechanism has been high overheads due to state-saving. We attack this problem by implementing the model using reverse computation. Here, the event processing routines are made reversible, which avoids having incrementally state-saving values that can be reverse computed, such as ++ and --. Destructive assignments of the form a = b are saved using a swap operation, which precludes the need for additional state space. In our performance study of this application, we find that speedups range from 1.5 to over 5 on four processors. Super-linear speedups are attributed to a slow memory subsystem and the increased availability of level-1 and level-2 cache when moving to a larger number of processors.