Boundedness, empty channel detection, and synchronization for communicating finite automata
Theoretical Computer Science
Analysis of a class of communicating finite state machines
Acta Informatica
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Theoretical Computer Science
Reversal-Bounded Multicounter Machines and Their Decision Problems
Journal of the ACM (JACM)
Reachability Analysis of Pushdown Automata: Application to Model-Checking
CONCUR '97 Proceedings of the 8th International Conference on Concurrency Theory
Binary Reachability Analysis of Discrete Pushdown Timed Automata
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Algorithms for Model Checking Pushdown Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Programs with Quasi-Stable Channels are Effectively Recognizable (Extended Abstract)
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Multiple Counters Automata, Safety Analysis and Presburger Arithmetic
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification in loosely synchronous queue-connected discrete timed automata
Theoretical Computer Science
| Hi-index | 5.23 |
A discrete pushdown timed automaton is a pushdown machine with integer-valued clocks. It has been shown recently that the binary reachability of a discrete pushdown timed automaton can be accepted by a two-tape pushdown acceptor with reversal-bounded counters. We improve this result by showing that the stack can be eliminated from the acceptor, i.e., the binary reachability can be accepted by a two-tape finite-state acceptor with reversal-bounded counters. We calso obtain similar results for other machine models. Our results can be used to verify certain properties concerning these machines that were not verifiable before using previous techniques. For example, we are able to formulate a subset of Presburger LTL that is decidable for satisfiability checking with respect to these machines. We also discuss the "boundedness problem" for reachability sets. Finally, we explain how the storage tape elimination technique can be applied to machines with real-valued clocks.