Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
IEEE Transactions on Computers
EURASIP Journal on Applied Signal Processing
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Artificial Intelligence
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
From Zhang neural network to Newton iteration for matrix inversion
IEEE Transactions on Circuits and Systems Part I: Regular Papers
MATLAB Simulation of Gradient-Based Neural Network for Online Matrix Inversion
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Novel HW architecture based on FPGAs oriented to solve the eigen problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable linear array architectures for matrix inversion using Bi-z CORDIC
Microelectronics Journal
Matrix inversion algorithm for linear array processor
Mathematical and Computer Modelling: An International Journal
Hi-index | 14.98 |
An array that inverts an n*n dense matrix in 5n-1 time units, including I/O time, is presented. The inversion algorithm consists of three phases and assumes that Gaussian elimination without pivoting can be applied. The array, which consists of 2n/sup 2/-n simple processing elements, implements and overlaps the execution of all three phases without any need for intermediate I/O or reconfiguration. An efficient data-steering technique which is well suited for feedback recurrences is utilized.