An improved systematic method for constructing systolic arrays from algorithms
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A Systolic Architecture for Fast Dense Matrix Inversion
IEEE Transactions on Computers
Signal Processing for Intelligent Sensor Systems
Signal Processing for Intelligent Sensor Systems
Digital Signal Processing: A Computer-Based Approach
Digital Signal Processing: A Computer-Based Approach
Advanced Digital Signal Processing and Noise Reduction
Advanced Digital Signal Processing and Noise Reduction
A hardware-efficient programmable FIR processor using input-data and tap folding
EURASIP Journal on Applied Signal Processing
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Design and realization of short range defence radar target tracking system based on DSP/FPGA
WSEAS TRANSACTIONS on SYSTEMS
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A new pipelined systolic array-based (PSA) architecture for matrix inversion is proposed. The pipelined systolic array (PSA) architecture is suitable for FPGA implementations as it efficiently uses available resources of an FPGA. It is scalable for different matrix size and as such allows employing parameterisation that makes it suitable for customisation for application-specific needs. This new architecture has an advantage of O(n) processing element complexity, compared to the O(n2) in other systolic array structures, where the size of the input matrix is given by n × n. The use of the PSA architecture for Kalman filter as an implementation example, which requires different structures for different number of states, is illustrated. The resulting precision error is analysed and shown to be negligible.