Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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This paper presents a high-level synthesis method for testable data paths with partial scan design based on acyclic structure. For a given scheduled data flow graph, we propose a heuristic method of operational unit binding and register binding to minimize the number of scan registers for acyclic structure without sacrifice of area overhead.