Vector access performance in parallel memories using skewed storage scheme
IEEE Transactions on Computers
Vector models for data-parallel computing
Vector models for data-parallel computing
A novel paradigm of parallel computation and its use to implement simple high-performance hardware
Future Generation Computer Systems - Special double issue: InfoJapan '90
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators
HICSS '97 Proceedings of the 30th Hawaii International Conference on System Sciences: Advanced Technology Track - Volume 5
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
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This paper introduces a powerful novel sequencer for controlling computational machines and for structured DMA (direct memory access) applications. It is mainly focused on applications using 2-dimensional memory organization, where most inherent speed-up is obtained thereof. A classification scheme of computational sequencing patterns and storage schemes is derived. In the context of application specific computing the paper illustrates its usefulness especially for data sequencing - recalling examples hereafter published earlier, as far as needed for completeness. The paper also discusses, how the new sequencer hardware provides substantial speed-up compared to traditional sequencing hardware use.