Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics

Authors:
X. Cai;K. Nabors;J. White
Affiliations:
-;-;-
Venue:
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Year:
1995

Citing 2
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Abstract

This paper describes an efficient implementation of a Galerkin based multipole-accelerated boundary element method for 3-D capacitance extraction of conductors in an arbitrary piecewise-constant dielectric medium. Results are presented to demonstrate that the Galerkin method is substantially more accurate than the commonly used collocation scheme for problems with dielectric interfaces. In addition, it is shown experimentally that for a given discretization, a careful implementation of the Galerkin method in a multipole-accelerated program is only slightly more computationally expensive than the collocation method.