Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
ACM SIGOPS Operating Systems Review
Real-time symbolic model checking for discrete time models
Theories and experiences for real-time system development
Verification Tools for Finite-State Concurrent Systems
A Decade of Concurrency, Reflections and Perspectives, REX School/Symposium
Applications of Multi-Terminal Binary Decision Diagrams
Applications of Multi-Terminal Binary Decision Diagrams
Task synchronization in real-time systems
Task synchronization in real-time systems
Computing timed transition relations for sequential cycle-based simulation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Modleing and Checking Networks of Communicating Real-Time Process
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
| Hi-index | 0.00 |
The verification of timing properties is an important task in the validation process of embedded and real time systems. Temporal logic model checking is one of the most successful techniques as it allows the complete automation of the verification. In this paper, we present a new approach to symbolic QCTL (Quantitative CTL) model checking. In contrast to previous approaches we use an intuitive QCTL semantics, provide an efficient model representation and the new algorithms require less iteration steps compared to translating the QCTL problem into CTL and using standard CTL model checking techniques. The new model checking algorithm is based on a MTBDD representation. Some experimental results show the efficiency of the new approach.