Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints

Authors:
Marek Perkowski;Alan Mishchenko;Anatoly Chebotarev
Affiliations:
-;-;-
Venue:
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Year:
1999

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Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach

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Abstract

Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraints solving, determinization, state machine minimization, structural mapping, functional decomposition of multi-valued logic functions and relations, and finally, FPGA mapping. In our approach, learning takes place on the level of constraint acquisition and functional decomposition rather than on the lower level of programming binary switches. Our learning strategy is based on the principle of Occam's Razor, facilitating generalization and discovery. We implemented several learning algorithms using DEC-PERLE-1 FPGA board.