Vision Chip Architecture Using General-Purpose Processing Elements for 1ms Vision System

Authors:
Takashi Komuro;Idaku Ishii;Masatoshi Ishikawa
Affiliations:
-;-;-
Venue:
CAMP '97 Proceedings of the 1997 Computer Architectures for Machine Perception (CAMP '97)
Year:
1997

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Abstract

This paper describes a vision chip architecture for high-speed vision systems that we propose. The chip has general-purpose processing elements (PEs) in a massively parallel architecture, with each PE directly connected to photo-detectors. Control programs allow various visual processing applications and algorithms to be implemented. A sampling rate of 1ms is enough to realize high-speed visual feedback for robot control. To integrate as many PEs as possible on a single chip a compact design is required, so we aim to create a very simple architecture. The sample design has been implemented into an FPGA chip; a full custom chip ha s also been designed and has been submitted for fabrication.