Microarchitecture of HaL's memory management unit

Authors:
D. C.-W. Chang;D. Lyon;C. Chen;L. Peng;M. Massoumi;M. Hakimi;S. Iyengar;E. Li;R. Remedios
Affiliations:
-;-;-;-;-;-;-;-;-
Venue:
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
Year:
1995

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Abstract

This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.