RVC - A Reconfigurable Coprocessor for Vector Processing Applications

Authors:
Jose C. Alves;Jose S. Matos
Affiliations:
-;-
Venue:
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Year:
1998

Citing 0
Cited 3

FAFNER-Accelerating Nesting Problems with FPGAs

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An FPGA-based VLIW processor with custom hardware execution

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Rapid VLIW processor customization for signal processing applications using combinational hardware functions

EURASIP Journal on Applied Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents RVC, a new reconfigurable platform for the implementation of custom computing machines, that is intended for vector coprocessors in low cost PC-based applications. The board includes 5 XILINX 4000E FPGAs and 4 fast static RAMs independently addressable, providing in each memory read cycle up to 64-bits of data to an application specific computation datapath. The design of this system was driven by the need to speedup a time consuming task in digital signal processing, making use of an application specific processor. Although executing integer arithmetic operations which tend to be efficiently performed by conventional processors, the vector architecture has demonstrated to reach more than an 8 times speedup with a 12.5 MHz clock frequency, compared to a PC Pentium running at 120 MHz.