Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application

Authors:
Ruth Sivilotti;Young Cho;Wen-King Su;Danny Cohen;Brian Bray
Affiliations:
-;-;-;-;-
Venue:
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Year:
1998

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Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

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Abstract

Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing throughput. In this paper, we describe an ATR algorithm implementation using FPGA accelerators. We will first describe the ATR algorithm that was implemented, the implementation on a single FPGA, how the FPGA nodes are connected to make a scalable system, and compare the performance to current scalable microprocessor-based implementations.