Précis: A Usercentric Word-Length Optimization Tool
IEEE Design & Test
An FPGA-based people detection system
EURASIP Journal on Applied Signal Processing
C is for circuits: capturing FPGA circuits as sequential code for portability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Clusters Versus FPGA for Parallel Processing of Hyperspectral Imagery
International Journal of High Performance Computing Applications
Towards real-time compression of hyperspectral images using virtex-iI FPGAs
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
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In this paper we present an implementation of the image compression routine SPIHT in reconfigurable logic. A discussion on why adaptive logic is required, as opposed to an ASIC, is provided along with background material on the image compression algorithm. We analyzed several Discrete Wavelet Transform architectures and selected the folded DWT design. In addition we provided a study on what storage elements are required for each wavelet coefficient.The paper uses a modification to the original SPIHT algorithm neededto parallelize the computation. The architecture of the SPIHT engine is based upon Fixed-Order SPIHT, developed specifically for use within adaptive hardware. For an N 脳 N image Fixed-Order SPIHT may be calculated in N2/4 Cycles. Square images which are powers of 2 up to 1024 脳 1024 are supported by the architecture. Our system was developed on an Annapolis Microsystems WildStar board populated with Xilinx Virtex-E parts.